Modern computer systems employ hierarchical memory designs that order storage devices in terms of access time and storage capacity. Cache memory systems are at the top of the hierarchy with the fastest access times and smallest storage capacities, such as shown in H. S. Stone, High-Performance Computer Architecture, Addison-Wesley (2d ed. 1990), pp. 29-87, the disclosure of which is hereby incorporated by reference. These are used to store the most frequently used sections of computer programs and data. Below these in the hierarchy, in order of decreasing access time and increasing storage capacity, are main memory and secondary storage. Memory caches are used to store two kinds of memory items staged from main memory: program instructions and data, the former of which is treated as read-only.
Cache memory systems are divided into two types: primary or level-1 caches, which are located on-chip as an integral part of the central processing unit (CPU), and secondary or level-2 caches, which are external to the CPU. Although providing faster access times, primary caches are of fixed storage capacity since size, power consumption and other engineering concerns with respect to the CPU can limit the primary cache design.
By contrast, since secondary caches are separate physical components from the CPU and are therefore not subject to such concerns, they can be increased in capacity by adding additional memory chips. Typically, static random access memory (SRAM) chips are used since they provide faster access times than conventional dynamic random access memory (DRAM) chips.
The capacities of secondary memory caches are generally significantly smaller than that of main memory and cache tags must be used to identify the main memory locations to which each cache entry corresponds. Consequently, two separate entities of memory chips are used whereby an entity can be one or more discrete memory chips with one entity storing the staged memory items and the other entity storing the cache tags. Examples of secondary memory caches employing separate entities of memory chips to store staged memory items and cache tags are disclosed in U.S. Pat. No. 5,210,845 to Crawford et al.; U.S. Pat. No. 5,339,399 to Lee et al.; U.S. Pat. No. 5,239,603 and U.S. Pat. No. 5,228,134, both to MacWilliams et al.
Problems resulting from the use of separate memory array structures for storing staged memory items and cache tags are increased architectural complexity, increased manufacturing costs and decreased operational speed by virtue of additional components.